1. Technical Field
The present invention relates to multi-chip packages, and more particularly, to a multi-chip package which can minimize the parasitic load of a package pin by adjusting the number of chips coupled to the package pin.
2. Description
In recent years, multi-chip package techniques for incorporating several memory chips into a single package have been widely used to increase memory capacity. However, in typical multi-chip packages, a parasitic load of a package pin is proportional to the number of embedded memory chips. An increased parasitic load impedes high-speed transmission of signals input to the package pin. Accordingly, it is imperative for the multi-chip packages to reduce the parasitic load of the package pin to at least the level of the parasitic load of a single chip.
FIG. 1 is a diagram of a memory bus coupled to N memory modules, each of which includes a memory device.
Referring to FIG. 1, N memory modules MM1, MM2, . . . , and MMN are mounted on N memory slots SLOT1, SLOT2, . . . , SLOTN. Each of the memory modules MM1, MM2, . . . , and MMN includes a memory device M1, M2, . . . , and MN, respectively. In FIG. 1, C represents an input capacitance of each of the memory modules MM1, MM2, . . . , and MMN.
High-performance memory systems are required to connect more memory per channel and simultaneously transmit signals faster. The amount of memory connected to one channel is limited in order to transmit signals at high speed.
The memory bus of FIG. 1 has an input capacitance of N×C, and the capacitance has the same effect as a load on signal transmission. That is, as N increases, it becomes difficult to transmit signals at high speed. In a typical stub-type memory bus, the number of slots for mounting memory modules is limited to four or less.
In general, while the number of memory slots is limited, to secure maximum memory capacity a memory module is manufactured by stacking several packages, or mounting several chips in a single package.
However, even if a stacked package or a multi-chip package is used, in a case that requires an increased transmission rate of signals, it is still difficult to transmit signals at high speed due to the entire load of signal transmission lines. Also, to secure signal compatibility, packages such as multi-chips may not be used and the number of memory slots is more strictly limited.
FIG. 2 is a diagram of a memory bus, in which the number of memory slots is limited to two.
Referring to FIG. 2, a first memory module MM1 includes two multi-chip devices M1 and M2, each of which includes two semiconductor chips. A second memory module MM2 includes two multi-chip devices M3 and M4, each of which also includes two semiconductor chips. Thus, the memory bus of FIG. 2 has an input capacitance of 8×C.
FIG. 3 is a diagram illustrating signal compatibility in relation to operations of the memory bus of FIG. 2.
In FIG. 3, the horizontal axis is the time axis and the vertical axis is the voltage axis.
It can be seen that both the first and second slots SLOT1 and SLOT2 exhibit low signal compatibility for write and read operations.
FIG. 4 is a diagram of a memory bus, in which the number of memory chips is reduced when compared to the memory module of FIG. 2.
FIG. 5 is a diagram illustrating signal compatibility in relation to operations of the memory bus of FIG. 4.
Referring to FIG. 4, a first memory module MM1 includes only two semiconductor chips M1 and M2, and a second memory module MM2 also includes only two semiconductor chips M3 and M4. Thus, the memory bus of FIG. 4 has an input capacitance of 4×C.
Referring to FIG. 5, when the input capacitance of the memory bus in FIG. 4 is reduced compared to the input capacitance of the memory bus in FIG. 2, then the signal compatibility is improved. Therefore, minimizing the parasitic load of a package pin improves the signal compatibility in a memory bus where signals are transmitted at high speed.
The present invention provides a multi-chip package which can minimize the parasitic load of a package pin and improve signal compatibility in a memory bus using memory modules supporting multiple semiconductor chips.
In accordance with one aspect of the present invention, a multi-chip device comprises: a package including a plurality of terminals; N semiconductor chips, each of which includes an input/output pad and an internal pad; and one or more first connectors, each first connector coupling the internal pad of one of the N semiconductor chips to the internal pad of another one of the N semiconductor chips. The input/output pad of a first one of the N semiconductor chips directly receives an input/output signal transmitted via a corresponding one of the terminals of the package, and a remaining (N−1) of the N semiconductor chips indirectly receive the input/output signal via the internal pads.
In accordance with another aspect of the present invention, a multi-chip device comprises: a package including a plurality of terminals; N semiconductor chips, each of which includes an input/output pad and an internal pad; and at least one first connector or second connector, each said connector coupling the internal pad of one of the N semiconductor chips to the internal pad of another one of the N semiconductor chips. The first connector includes a first bump, and the second connector includes a second bump and a Through Silicon Via (TSV). The input/output pad of a first one of the N semiconductor chips directly receives an input/output signal transmitted via a corresponding one of the terminals of the package, and a remaining (N−1) of the N semiconductor chips indirectly receive the input/output signal via the internal pads.
In accordance with still another aspect of the present invention, a multi-chip device comprises: a package including a plurality of terminals; N semiconductor chips, each of which includes an input/output pad and an internal pad; and one or more first connectors, each first connector coupling one of the internal pad and the input/output pad of one of the N semiconductor chips to one of the internal pad and the input/output pad of another one of the N semiconductor chips. The input/output pad of a first one of the N semiconductor chips directly receives an input/output signal transmitted via a corresponding one of the terminals of the package. The internals pads of another X of the N semiconductor chips indirectly receive the input/output signal, and a remaining (N−X−1) of the N semiconductor chips indirectly receive the input/output signal via the input/output pads.